1. Field of the Invention
The present invention is related to a method of manufacturing liquid crystal display, more particularly to a method simplifying manufacturing process thereof.
2. Description of the Related Art
A Liquid Crystal Display, hereinafter LCD has been used as a display device for digital clock and calculator, recently used for television set and monitors also. More particularly, thin film transistor LCD, hereinafter TFT-LCD is likely used for display devices having a high resolution characteristic and large sized screen such as the Cathode Ray Tube (CRT) since the TFT-LCD has the characteristics of fast response time and is suitable for a device having a high-number of pixel element.
Meanwhile, an aperture ratio, a ratio of substantively transmitted light against the entire dimension of a pixel electrode has an effect on the displaying characteristics of LCDs. In general, the displaying characteristics of LCDs is enhanced when the aperture ratio is high. Accordingly, an LCD having an enhanced aperture ratio, for example FIG. 1 has proposed.
FIG. 1 is a plane view showing an LCD unit cell having a high aperture ratio according to conventional arts.
As shown in Fig.1, a gate line 2 and a storage line 4 are formed parallel in a row. A data line 8 is formed perpendicular to the gate line 2 and the storage line 4. The storage line 4 includes two parts, a first part 4a serving as a common signal line and a second part 4b serving as a storage capacitor, herein width of the second part 4b is larger than that of the first part 4a.
A TFT 15 is formed at an intersection of the gate line 2 and the data line 8. Herein, the TFT 15 includes a gate electrode extended from the gate line 2, a semiconductor layer 6 disposed on the upper of the gate electrode with sandwiching a gate insulating layer (not shown) and source and drain electrodes 9a, 9b both being overlapped with both side portions of the semiconductor layer 6 respectively.
A pixel electrode 12 of transparent metal such as Indium Tin Oxide, hereinafter ITO is formed at a pixel area defined by the gate line 2 and the data line 8. Herein, as shown in the drawings, the pixel electrode 12 overlaps with portions of the gate line 12 and the data line 8 and is connected to the source electrode 9a.
FIG. 2 is a cross-sectional view taken along the line II--II of FIG. 1. With reference to this drawing, a method of manufacturing liquid crystal display will be discussed.
A metal layer for gate line is deposited on a transparent insulating substrate, for example a glass substrate 20. A gate electrode 2a and a storage line 4 are formed by patterning the metal layer for gate line. A gate insulating layer 3 is deposited on the glass substrate 20 to covers the gate electrode 2a and the storage line 4. A pattern of semiconductor layer 6 is formed on the gate insulating layer over the gate electrode 2a.
A metal layer for data line is deposited on the semiconductor layer 6 and the gate insulating layer 3. A data line 8 and source and drain electrodes 9a and 9b are formed by patterning the metal layer for data line. As a result, a TFT 15 including the gate electrode 2a, the gate insulating layer 3, the semiconductor layer 6, the source and the drain electrodes is formed on a predetermined portion of the glass substrate 20.
An organic insulating layer 10 is coated over the above structure and a contact hole 19 is formed on the organic insulating layer 10 to expose the source electrode 9a by conventional photolithography techniques.
An ITO metal layer is deposited within the contact hole 19 and on the organic insulating layer 10, and a pixel electrode 12 is formed by patterning the ITO metal layer. The pixel electrode 12 overlaps with portions of the gate line and the data line 8 and is connected to the source electrode 9a.
As described above, the organic insulating layer 10 is used for insulating the data line 8 and the pixel electrode 12. More particularly, a material having lower dielectric constant is used so as to prevent deterioration of LCD displaying characteristics. If the material having lower dielectric constant is used as the organic insulating layer 10, because parasitic capacitance Cp between the data line 8 and the pixel electrode 12 which has overlapped with each other has nearly meaningless, this parasitic capacitance has no effect on the LCD driving.
Because in the LCD in FIG.1, the pixel electrode 12 is formed to be overlapped with the data line 8, the LCD having unit cell of the above structure has a superior aperture ratio to a conventional LCD whose pixel electrode is disposed within the pixel area.
However, the structure has also the drawback of deterioration in LCD displaying characteristics since capacitance C decreases due to use of an organic insulating layer of lower dielectric constant between the storage electrode and the pixel electrode. This is not a preferable structure since additional power supply is required for obtaining a desirable capacitance in the above LCD structure.
In the mean time, a conventional LCD having a double-layered ITO electrode structure which improves the aperture ratio and simultaneously prevents capacitance deterioration is proposed.
FIG. 3 is a plane view showing a unit cell of the LCD having double-layered ITO electrode structure.
As shown in the drawing, a gate line 22 and a storage line 24 are formed parallel in a row, and a data line 28 is formed perpendicular to the gate line 22 and the storage line 24. The storage line 24 includes a first part 24a and a second part 24b, both having a different width from each other.
A TFT 35 including a gate electrode extended from the gate line 22, a gate insulating layer (not shown) , a semiconductor layer 26, source and drain electrodes 29a, 29b is formed at an intersection of the gate line 22 and the data line 28.
A first ITO electrode 30, hereinafter a bottom ITO is formed within a pixel area defined by the gate line 22 and the data line 28. A second ITO electrode 36, hereinafter a top ITO is formed to overlap with portions of the gate line 22 and the data line 28 and the top ITO is connected to the source electrode 29a. The top ITO is not yet connected to the second part 24b of the storage line 24 and the source electrode 29a.
The reference numeral 32 not described, is an additional conductive pattern for easily obtaining capacitance.
FIG. 4 is a cross-sectional view take along the line IV--IV of FIG. 3. With reference to the drawing, a method of manufacturing the same will be described.
A metal layer for gate line is formed on a glass substrate 40, and a gate line (not shown) and a storage line 24 is formed by patterning the metal layer for gate line. A gate insulating layer 25 is disposed on the glass substrate 40 to cover the storage line 24. As the gate insulating layer 25, a silicon oxide film SiO2 25a and a silicon nitride film SiON 25b are successively deposited in stack.
A first contact hole 27 is formed in the gate insulating layer 25 so as to expose the first part 24a of the storage line 24. An ITO metal layer is deposited within the first contact hole 27 and on the gate insulating layer 25. A bottom ITO 30 is formed within the pixel area by patterning the ITO metal layer. A data line 28 is formed on the gate insulating layer 25 by a conventional process. At this time, a conductive pattern 32 is also formed on the gate insulating layer 25 over the second part 24b of the storage line 24.
Not shown in the drawing, a semiconductor layer is formed on a predetermined region prior to form the data line 28 and source and drain electrodes together with the date line 28 also formed so that a TFT is formed at an intersection of the gate line 22 and the data line 28.
Continuously, an organic insulating layer 34 having lower dielectric constant is formed on the entire surface of the substrate. A second contact hole 39 is formed in the organic insulating layer 34 so as to expose the conductive pattern 32. An ITO metal layer is formed within the second contact hole 39 and on the organic insulating layer 34, and a top ITO 36 is formed by patterning the ITO metal layer. The top ITO 36 is formed over the entire pixel area so as to be overlap with portions of the gate line 22 and the data line 28.
The LCD having a double-layered structure obtains its main capacitance Cm between the top ITO 36 and the storage line 24 while sandwiching the gate insulating layer 25 and auxiliary capacitance Ca between the bottom ITO 30 in contact with the storage line 24 and the top ITO 36 while sandwiching the organic insulating layer 34. Consequently, decrease in capacitance caused by sandwiching the organic insulating layer 34 having lower dielectric constant, is prevented. The LCD having the above structure can obtain a high aperture ratio and a high capacitance.
However, the LCD capable of preventing the capacitance decrease also has a drawback that an additional manufacturing process for connecting the storage line and the bottom ITO, i. e. etching step is required. Especially, the etching step needs further etching mask, which leads to an increase in the manufacturing cost.